8 channel, 16 bit Verilog Multiplexer
[code title=”mux_8to1_16bit.v” collapse=”true”] // 8 channel mux // BK Turley `timescale 1ns/100ps module mux_8to1_16bit(out, sel, in0, in1, in2, in3, in4, […]
Verilog model of a control unit for the SEP (Simple Educational Processor)
[code title=”View Code: sep_cu.v” collapse=”true”] module cu(clk, reset, IRin, C, SC_Val); input clk, reset; input [15:0] IRin; output [14:0] C; […]