16 bit ALU Verilog design
[code title=”sep_alu.v Main module” collapse=”true”] //B Turley //16 bit ALU `timescale 1ns/100ps module sep_alu(Y, cout16, cout15, rightout, leftout, A, B, […]
8 channel, 16 bit Verilog Multiplexer
[code title=”mux_8to1_16bit.v” collapse=”true”] // 8 channel mux // BK Turley `timescale 1ns/100ps module mux_8to1_16bit(out, sel, in0, in1, in2, in3, in4, […]
Verilog 16 bit register with testbench.
[code title=”reg_16bit.v code” collapse=”true”]//16 bit Register by B Kyle Turley //Verilog `timescale 1ns/100ps module reg_16bit (out, in, load, clear, clk); […]
Verilog Clock and Oscillator
The clock signal is essential when designing sequential circuits, the following two code examples demonstrate how to produce a clock […]